Integrated Device Technology Senior Electronic Design Engineer Salary

Integrated Device Technology Senior Electronic Design Engineer average salary is $99,379, median salary is $97,864 with a salary range from $84,302 to $114,109.
Integrated Device Technology Senior Electronic Design Engineer salaries are collected from government agencies and companies. Each salary is associated with a real job position. Integrated Device Technology Senior Electronic Design Engineer salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.

Low: 84,302

Average: 99,379

Median: 97,864

High: 114,109

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Jobtitle	Company	Salary	City	Year
Senior Electronic Design Engineer	Integrated Device Technology	$ 97,864	Tempe, AZ, 85280	10/01/2012
Senior Electronic Design Engineer	Integrated Device Technology	$ 108,000	San Jose, CA, 95101	10/01/2012
Senior Electronic Design Engineer	Integrated Device Technology	$ 84,302	Duluth, GA, 30026	03/02/2013
Senior Electronic Design Engineer	Integrated Device Technology	$ 87,318	Duluth, GA, 30026	03/02/2013
Senior Electronic Design Engineer	Integrated Device Technology	$ 108,077	San Jose, CA, 95101	09/15/2013
Senior Electronic Design Engineer	Integrated Device Technology	$ 114,109	Irvine, CA, 92602	09/20/2013
Senior Electronic Design Engineer	Integrated Device Technology	$ 114,109	Irvine, CA, 92602	05/31/2013
Senior Electronic Design Engineer	Integrated Device Technology	$ 92,545	Duluth, GA, 30026	08/20/2014
Senior Electronic Design Engineer	Integrated Device Technology	$ 95,000	Tempe, AZ, 85280	09/01/2015
Senior Electronic Design Engineer	Integrated Device Technology	$ 92,518	Tempe, AZ, 85280	09/01/2015
Senior Electronic Design Engineer	Integrated Device Technology	$ 99,323	Duluth, GA, 30026	08/20/2017

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Integrated Device Technology Senior Electronic Design Engineer salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.


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