SOC Implementation Engineer (Portland, Chandler, Boxborough) All Levels!

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm’s SoC implementation team is seeking talented Engineers to work on synthesis, timing constraints, formal verification, power analysis, STA and functional ECO activities to bridge between RTL and physical design for premium tier Snapdragon chips. This is a great opportunity to join a fast-paced implementation team responsible for SoCs in sub-7nm nodes in mobile/AI/XR space. An absolute minimum of 3 years of experience is required in tools such as Design Compiler (DC-NXT), Fusion Compiler, Genus-ISpatial, Primetime, Conformal Low Power, LEC and Formality, ideally with exposure to SoC top level challenges. Scripting skills in TCL, PERL and/or Python are a bonus

Principal Duties & Responsibilities

• Develop constraints, run physical power-aware synthesis, low power multi-voltage domain checks, static timing analysis (STA) and power-aware formal verification

• Work closely with RTL design, physical design, low power and automation teams to optimize area, performance and power

• Generate, review and validate clock domain crossing, design constraints to achieve timing closure of complex SOC cores

• Tabulate metrics results for QoR comparison (area, power and performance). Analyze trade offs in area, power and performance to get an optimal netlist.

• Conformal ECO for doing complex functional ECOs.

Basic Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or closely related field.

• 3-5 years of experience with Synthesis with Genus/DC, STA

Preferred Qualifications:

• Master's degree in Computer Engineering, Electrical Engineering, or closely related field.

• 5+ years of experience with Low power implementation techniques, DC/Genus Synthesis and STA, constraints management

• 5+ years of experience with Perl/TCL scripting

Minimum Qualifications:

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, or related work experience.

OR

Master's degree in Science, Engineering, or related field and 1+ years of ASIC design, verification, or related work experience.

OR

PhD in Science, Engineering, or related field.

Qualcomm is committed to hiring and supporting individuals with disabilities. Although this role has some expected physical activity, an inability to perform one or more of the listed physical requirements should not deter otherwise qualified applicants from applying. We will work with you throughout the application and onboarding process to provide reasonable accommodations. Examples of expected physical activity include: frequently transporting between offices, buildings, and campuses up to ½ mile; frequently transporting and installing equipment up to 5 lbs.; performing tasks at various heights (e.g., standing or sitting); monitoring and utilizing computers and test equipment for more than 6 hours a day; and continuous communication which includes the comprehension of information with colleagues, customers, and vendors both in person and remotely.

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

If you would like more information about this role, please contact Qualcomm Careers (http://www.qualcomm.com/contact/corporate) .

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

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