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Lead Asic Design Verification Engineers (asic Dv E Salary

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Lead Asic Design Verification Engineers (asic Dv E average salary is $104,853, median salary is $104,853 with a salary range from $104,706 to $105,000.
Lead Asic Design Verification Engineers (asic Dv E salaries are collected from government agencies and companies. Each salary is associated with a real job position. Lead Asic Design Verification Engineers (asic Dv E salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Total 2 Salaries. Sorted by Date, page 1
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Company Salaries City Year More info
Smartplay 105,000-105,000 San Diego, CA, 92101 2014 Smartplay Lead Asic Design Verification Engineers (asic Dv E Salaries (4)
Lead Asic Design Verification Engineers (asic Dv E San Diego, CA Salaries
Smartplay 104,706-105,000 San Jose, CA, 95101 2014 Smartplay Lead Asic Design Verification Engineers (asic Dv E Salaries (4)
Lead Asic Design Verification Engineers (asic Dv E San Jose, CA Salaries
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Lead Asic Design Verification Engineers (asic Dv E salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.

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