- Low
- 21,882
- Average
- 103,560
- Median
- 99,000
- High
- 1,250,000
Staff Asic Design Verification Engineer (asic Dv Engr) San Jose, CA Salary
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Staff Asic Design Verification Engineer (asic Dv Engr) San Jose, CA average salary is $103,560, median salary is $99,000 with a salary range from $21,882 to $1,250,000.
Staff Asic Design Verification Engineer (asic Dv Engr) San Jose, CA salaries are collected from government agencies and companies. Each salary is associated with a real job position. Staff Asic Design Verification Engineer (asic Dv Engr) San Jose, CA salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Staff Asic Design Verification Engineer (asic Dv Engr) San Jose, CA salaries are collected from government agencies and companies. Each salary is associated with a real job position. Staff Asic Design Verification Engineer (asic Dv Engr) San Jose, CA salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
| Jobtitle | Company | Salary | City | Year |
| Staff Asic Design Verification Engineer (asic Dv Engr) | Smartplay | $ 151,000 | San Jose, CA, 95101 | 10/03/2014 |
| Staff Asic Design Verification Engineer (asic Dv Engr) | Smartplay | $ 151,000 | San Jose, CA, 95101 | 10/03/2014 |
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Staff Asic Design Verification Engineer (asic Dv Engr) San Jose, CA salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.
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