- Low
- 75,000
- Average
- 120,000
- Median
- 140,000
- High
- 145,000
Sr. Asic Design Verification Engineer Salary
92
21
71
Sr. Asic Design Verification Engineer average salary is $120,000, median salary is $140,000 with a salary range from $75,000 to $145,000.
Sr. Asic Design Verification Engineer salaries are collected from government agencies and companies. Each salary is associated with a real job position. Sr. Asic Design Verification Engineer salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Sr. Asic Design Verification Engineer salaries are collected from government agencies and companies. Each salary is associated with a real job position. Sr. Asic Design Verification Engineer salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
| Company | Salaries | City | Year | More info |
| Severn Trent Water Purification | 140,000-145,000 | Santa Clara, CA, 95050 | 2018 | Severn Trent Water Purification Sr. Asic Design Verification Engineer Salaries (2) Sr. Asic Design Verification Engineer Santa Clara, CA Salaries |
| Zf Sachs Automotive Of America | 75,000-75,000 | Sunnyvale, CA, 94086 | 2013 | Zf Sachs Automotive Of America Sr. Asic Design Verification Engineer Salaries (1) Sr. Asic Design Verification Engineer Sunnyvale, CA Salaries |
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Sr. Asic Design Verification Engineer salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.
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