- Low
- 54,000
- Average
- 90,877
- Median
- 106,630
- High
- 112,000
Engineer, Staff Asic Design/verification Salary
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61
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Engineer, Staff Asic Design/verification average salary is $90,877, median salary is $106,630 with a salary range from $54,000 to $112,000.
Engineer, Staff Asic Design/verification salaries are collected from government agencies and companies. Each salary is associated with a real job position. Engineer, Staff Asic Design/verification salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
Engineer, Staff Asic Design/verification salaries are collected from government agencies and companies. Each salary is associated with a real job position. Engineer, Staff Asic Design/verification salary statistics is not exclusive and is for reference only. They are presented "as is" and updated regularly.
| Company | Salaries | City | Year | More info |
| Dizer | 54,000-54,000 | Philadelphia, PA, 19019 | 2017 | Dizer Engineer, Staff Asic Design/verification Salaries (1) Engineer, Staff Asic Design/verification Philadelphia, PA Salaries |
| Marvell Semiconductor | 106,630-106,630 | Santa Clara, CA, 95050 | 2014 | Marvell Semiconductor Engineer, Staff Asic Design/verification Salaries (2) Engineer, Staff Asic Design/verification Santa Clara, CA Salaries |
| Marvell Semiconductor | 112,000-112,000 | Santa Clara, CA, 95050 | 2013 | Marvell Semiconductor Engineer, Staff Asic Design/verification Salaries (2) Engineer, Staff Asic Design/verification Santa Clara, CA Salaries |
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Engineer, Staff Asic Design/verification salary is full-time annual starting salary. Intern, contractor and hourly pay scale vary from regular exempt employee. Compensation depends on work experience, job location, bonus, benefits and other factors.
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商标专利专员工资知识产权工程师/专利工程师工资资深知识产权工程师工资 Engineer, Staff Asic Design... Jobs
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